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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TNETV6446AINZWT 데이터시트(PDF) 165 Page - Texas Instruments |
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TNETV6446AINZWT 데이터시트(HTML) 165 Page - Texas Instruments |
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165 / 227 page  TMS320DM6446 www.ti.com SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010 6.13.1.5 Histogram The histogram module accepts raw image/video data and bins the pixels on a value (and color separate) basis. The value of the pixel itself is not stored, but each bin contains the number of pixels that are within the appropriate set range. The source of the raw data for the histogram is typically a CCD/CMOS sensor (via the CCDC module) or optionally from DDR2. The following features are supported by the histogram module. • Up to four regions/areas. • Separate horizontal/vertical start and end position for each region. • Pixels from overlapping regions are accumulated into the highest priority region. The priority is: region0 > region1 > region2 > region3. • Interface to conventional Bayer pattern. Each region can accumulate either 3 or 4 colors. • 32, 64, 128, or 256 bins per color per region. • 32, 64, or 128 bins per color for 2 regions. • 32 or 64 bins per color for 3 or 4 regions. • Automatic clear of histogram RAM after an ARM read. • Saturation of the pixel count if the count exceeds the maximum value (each memory location is 20-bit wide). • Downshift ranging from 0 to 7 bits (maximum bin range 128). • The last bin (highest range of values) will accumulate any value that is higher than the lower bound. The Histogram register memory mapping is shown in Table 6-52. Table 6-52. Histogram Register Descriptions HEX ADDRESS RANGE REGISTER ACRONYM DESCRIPTION 0x01C7 1000 PID Peripheral Revision and Class Information Register 0x01C7 1004 PCR Peripheral Control Register 0x01C7 1008 HIST_CNT Histogram Control Bits Register 0x01C7 100C WB_GAIN White/Channel Balance Settings Register 0x01C7 1010 R0_HORZ Region 0 Horizontal Information Register 0x01C7 1014 R0_VERT Region 0 Vertical Information Register 0x01C7 1018 R1_HORZ Region 1 Horizontal Information Register 0x01C7 101C R1_VERT Region 1 Vertical Information Register 0x01C7 1020 R2_HORZ Region 2 Horizontal Information Register 0x01C7 1024 R2_VERT Region 2 Vertical Information Register 0x01C7 1028 R3_HORZ Region 3 Horizontal Information Register 0x01C7 102C R3_VERT Region 3 Vertical Information Register 0x01C7 1030 HIST_ADDR Histogram Address for Data to be Read Register 0x01C7 1034 HIST_DATA Histogram Data That is Read From the Memory Register 0x01C7 1038 RADD Read Address From DDR2 Memory Register 0x01C7 103C RADD_OFF Read Address Offset for Each Line in the DDR2 Memory Register 0x01C7 1040 H_V_INFO Horizontal/Vertical Information Register (Horizontal/Vertical Number of Pixels When Data is Read From DDR2 Memory Information Register) Copyright © 2005–2010, Texas Instruments Incorporated Peripheral and Electrical Specifications 165 Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 |
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