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TNETV6446AINZWT 데이터시트(PDF) 210 Page - Texas Instruments |
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TNETV6446AINZWT 데이터시트(HTML) 210 Page - Texas Instruments |
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210 / 227 page ![]() MRCLK (Input) 1 2 MRXD3−MRXD0, MRXDV, MRXER (Inputs) 1 MTCLK (Input) MTXD3−MTXD0, MTXEN (Outputs) TMS320DM6446 SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010 www.ti.com Table 6-96. Timing Requirements for EMAC MII Receive 10/100 Mbit/s(1) (see Figure 6-70) A-513, -594, NO. UNIT -810 MIN MAX 1 tsu(MRXD-MRCLKH) Setup time, receive selected signals valid before MRCLK high 8 ns 2 th(MRCLKH-MRXD) Hold time, receive selected signals valid after MRCLK high 8 ns (1) Receive selected signals include: MRXD3-MRXD0, MRXDV, and MRXER. Figure 6-70. EMAC Receive Interface Timing Table 6-97. Switching Characteristics Over Recommended Operating Conditions for EMAC MII Transmit 10/100 Mbit/s(1) (see Figure 6-71) A-513, -594, NO. UNIT -810 MIN MAX 1 td(MTCLKH-MTXD) Delay time, MTCLK high to transmit selected signals valid 5 25 ns (1) Transmit selected signals include: MTXD3-MTXD0, and MTXEN. Figure 6-71. EMAC Transmit Interface Timing 210 Peripheral and Electrical Specifications Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 |
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