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TNETV6446AINZWT 데이터시트(PDF) 220 Page - Texas Instruments

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부품명 TNETV6446AINZWT
상세설명  Digital Media System-on-Chip
PDF  227 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI1 - Texas Instruments

TNETV6446AINZWT 데이터시트(HTML) 220 Page - Texas Instruments

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VLYNQ_CLK
VLYNQ_TXD[3:0]
VLYNQ_RXD[3:0]
1
2
3
4
Data
Data
TMS320DM6446
SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010
www.ti.com
Table 6-111. Switching Characteristics Over Recommended Operating Conditions for Transmit Data for
the VLYNQ Module (see Figure 6-78)
A-513,
-594,
NO.
PARAMETER
UNIT
-810
MIN
MAX
Delay time, VLYNQ_CLK high to VLYNQ_TXD[3:0] invalid
1
ns
[SLOW Mode]
1
td(VCLKH-TXDI)
Delay time, VLYNQ_CLK high to VLYNQ_ TXD[3:0] invalid
0.5
ns
[FAST Mode]
2
td(VCLKH-TXDV)
Delay time, VLYNQ_CLK to VLYNQ_TXD[3:0] valid
9.75
ns
Table 6-112. Timing Requirements for Receive Data for the VLYNQ Module (see Figure 6-78)
A-513,
-594,
NO.
UNIT
-810
MIN
MAX
RTM disabled, RTM sample = 3
0.8
ns
RTM enabled, RXD Flop = 0
2.2
ns
RTM enabled, RXD Flop = 1
1.9
ns
RTM enabled, RXD Flop = 2
1.4
ns
Setup time, VLYNQ_RXD[3:0] valid before
3
tsu(RXDV-VCLKH)
RTM enabled, RXD Flop = 3
0.8
ns
VLYNQ_CLK high
RTM enabled, RXD Flop = 4
0.4
ns
RTM enabled, RXD Flop = 5
0.1
ns
RTM enabled, RXD Flop = 6
-0.2
ns
RTM enabled, RXD Flop = 7
-0.4
ns
RTM disabled, RTM sample = 3
2
ns
RTM enabled, RXD Flop = 0
0.6
ns
RTM enabled, RXD Flop = 1
1.0
ns
RTM enabled, RXD Flop = 2
1.5
ns
Hold time, VLYNQ_RXD[3:0] valid after
4
th(VCLKH-RXDV)
RTM enabled, RXD Flop = 3
2.0
ns
VLYNQ_CLK high
RTM enabled, RXD Flop = 4
2.5
ns
RTM enabled, RXD Flop = 5
3.0
ns
RTM enabled, RXD Flop = 6
3.5
ns
RTM enabled, RXD Flop = 7
4.0
ns
Figure 6-78. VLYNQ Transmit/Receive Timing
220
Peripheral and Electrical Specifications
Copyright © 2005–2010, Texas Instruments Incorporated
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Product Folder Link(s): TMS320DM6446



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