TMS320VC5416 datasheet(6/98 Pages) TI1

6 / 98 page

TMS320VC5416

Fixed-Point Digital Signal Processor

SPRS095P – MARCH 1999 – REVISED OCTOBER 2008

www.ti.com

5-15

Reset and BIO Timings

......................................................................................................... 73

5-16

Interrupt Timing

.................................................................................................................. 74

5-17

MP/MC Timing

................................................................................................................... 74

5-18

Instruction Acquisition (IAQ) and Interrupt Acknowledge (IACK) Timings

................................................ 75

5-19

External Flag (XF) Timing

...................................................................................................... 76

5-20

TOUT Timing

..................................................................................................................... 76

5-21

McBSP Receive Timings

....................................................................................................... 78

5-22

McBSP Transmit Timings

....................................................................................................... 79

5-23

McBSP General-Purpose I/O Timings

........................................................................................ 80

5-24

McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0

.................................................... 81

5-25

McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0

.................................................... 82

5-26

McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1

.................................................... 83

5-27

McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1

.................................................... 84

5-28

Using HDS to Control Accesses (HCS Always Low)

........................................................................ 87

5-29

Using HCS to Control Accesses

............................................................................................... 88

5-30

HINT Timing

...................................................................................................................... 88

5-31

GPIOx Timings

................................................................................................................... 88

5-32

Nonmultiplexed Read Timings

................................................................................................. 90

5-33

Nonmultiplexed Write Timings

................................................................................................. 91

5-34

HRDY Relative to CLKOUT

.................................................................................................... 91

List of Figures

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