TMS320VC5416 datasheet(64/98 Pages) TI1

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5.5.3

I/O Read

td(CLKL-IOSH)

th(D)R

td(CLKL-A)

CLKOUT

A[22:0]

(see Note A)

D[15:0]

IOSTRB

R/W

(see Note A)

td(CLKL-IOSL)

tsu(D)R

ta(A)M1

td(CLKL-A)

TMS320VC5416

Fixed-Point Digital Signal Processor

SPRS095P – MARCH 1999 – REVISED OCTOBER 2008

www.ti.com

Table 5-10 and Table 5-11 assume testing over recommended operating conditions, IOSTRB = 0, and

H = 0.5tc(CO) (see Figure 5-8).

Table 5-10. I/O Read Timing Requirements

5416-120

5416-160

UNIT

MIN

MAX

ta(A)M1

Access time, read data access from address valid, first read access(1)

4H – 9

tsu(D)R

Setup time, read data valid before CLKOUT low

th(D)R

Hold time, read data valid after CLKOUT low

(1)

Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.

Table 5-11. I/O Read Switching Characteristics

5416-120

5416-160

PARAMETER

UNIT

MIN

MAX

td(CLKL-A)

Delay time, CLKOUT low to address valid(1)

– 1

td(CLKL-IOSL)

Delay time, CLKOUT low to IOSTRB low

– 1

td(CLKL-IOSH)

Delay time, CLKOUT low to IOSTRB high

(1)

Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.

Figure 5-8. Parallel I/O Port Read (IOSTRB = 0)

Electrical Specifications

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