TMS320VC5416 datasheet(89/98 Pages) TI1

89 / 98 page

5.5.11.2

HPI16 Mode

TMS320VC5416

Fixed-Point Digital Signal Processor

www.ti.com

SPRS095P – MARCH 1999 – REVISED OCTOBER 2008

Table 5-34 and Table 5-35 assume testing over recommended operating conditions and P = 0.5 *

processor clock (see Figure 5-32 through Figure 5-34). In the following tables, DS refers to the logical OR

of HCS, HDS1, and HDS2, and HD refers to any of the HPI data bus pins (HD0, HD1, HD2, etc.). These

timings are shown assuming that HDS is the signal controlling the transfer. See the TMS320C54x DSP

Reference Set,Volume 5: Enhanced Peripherals (literature number SPRU302) for additional information.

Table 5-34. HPI16 Mode Timing Requirements

5416-120

5416-160

UNIT

MIN

MAX

tsu(HBV-DSL)

Setup time, HR/W valid before DS falling edge

th(DSL-HBV)

Hold time, HR/W valid after DS falling edge

tsu(HAV-DSH)

Setup time, address valid before DS rising edge (write)

tsu(HAV-DSL)

Setup time, address valid before DS falling edge (read)

–(4P– 6)(1)

th(DSH-HAV)

Hold time, address valid after DS rising edge

tw(DSL)

Pulse duration, DS low

tw(DSH)

Pulse duration, DS high

Reads

10P + 30(1)

Memory accesses with no DMA activity.

Writes

10P + 10(1)

Reads

16P + 30(1)

Cycle time, DS rising edge to

Memory accesses with 16-bit DMA

tc(DSH-DSH)

next DS rising edge

activity.

Writes

16P + 10(1)

Reads

24P + 30(1)

Memory accesses with 32-bit DMA

activity.

Writes

24P + 10(1)

tsu(HDV-DSH)W

Setup time, HD valid before DS rising edge

th(DSH-HDV)W

Hold time, HD valid after DS rising edge, write

(1)

P = 0.5 * processor clock.

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