| 전자부품 데이터시트 검색엔진 |
|
L7987 데이터시트(PDF) 25 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
L7987 데이터시트(HTML) 25 Page - STMicroelectronics |
|
25 / 37 page ![]() DocID025589 Rev 3 25/37 L7987 Application information 37 5.4.1 Type II compensation network If the equivalent series resistance (RES) of the output capacitor introduces a zero with a frequency lower than the desired bandwidth (that is: 2 • RES • CO > 1/BW), this zero helps stabilize the loop. Electrolytic capacitors show non-negligible ESR (> 30 m typically), so with this kind of output capacitor the type II network combined with the zero of the ESR allows to stabilize the loop. Figure 11. Type II compensation network The type II compensation network transfer function, from VOUT to COMP, is computed in Equation 20. Equation 20 Equation 21 The following suggestions can be followed for a quite common compensation strategy, assuming that CP << CF. Starting from Equation 19, in case of type II compensation network and electrolytic output capacitors the control loop gain module at s = 2 • FBW allows to fix the RF/RU ratio: Equation 22 1 0 1 2 1 2 2 1 1 ) ( 1 1 ) ( ) ( P P Z F P F P F F F U U F COMPII f s f s f s R C sC C C s R sC R R s Z s G F P F P U P F P F F Z R C C f R C C f R C f 2 1 ; 2 1 ; 2 1 1 0 1 1 1 1 ) 2 ( 2 , BW U F zESR LC FF BW II LOOP f R R f f k f s G |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |