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ST1S14 데이터시트(PDF) 19 Page - STMicroelectronics |
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ST1S14 데이터시트(HTML) 19 Page - STMicroelectronics |
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19 / 46 page ![]() DocID17977 Rev 2 19/46 ST1S14 Closing the loop Equation 10 whereas the zero is defined as: Equation 11 The embedded compensation network is RC=200 K, CP=24 pF, CC=211 pF and CO can be considered negligible, so the singularities are: Equation 12 6.3 Voltage divider The contribution of a simple voltage divider is: Equation 13 Figure 11. Leading network example A small signal capacitor in parallel to the upper resistor (see Figure 11.) of the voltage divider implements a leading network (fzero < fpole), sometimes necessary to improve the system phase margin: Equation 14 f P HF 1 2 π R c C 0 C p + () ⋅⋅ ⋅ ------------------------------------------------------------ = F Z 1 2 π R c C c ⋅⋅ ⋅ ------------------------------------------ = f Z 3 77 kHz , = f P LF 301 Hz , = f P HF 33 16 kHz , = G DIV s () R 2 R 1 R 2 + -------------------- = |
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