| 전자부품 데이터시트 검색엔진 |
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ST1S14 데이터시트(PDF) 20 Page - STMicroelectronics |
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ST1S14 데이터시트(HTML) 20 Page - STMicroelectronics |
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20 / 46 page ![]() Closing the loop ST1S14 20/46 DocID17977 Rev 2 where: 6.4 Total loop gain In summary, the open loop gain can be expressed as: Equation 15 Example: VIN = 12 V, VOUT = 3.3 V, ROUT = 2 Ω. The resistor divider is R1=5.6 K, R2=3.3 K. CR1=150 nF implements a leading network (fZ=190 kHz, fP=510 kHz). Selecting L = 8.2 µH, COUT = 100 µF, and ESR = 75 mΩ, the gain and phase bode diagrams are plotted respectively in Figure 12 and 13 over input voltage range (VIN=6 V to 48 V, IOUT=3 A). Figure 12. Module plot G DIV s () R 2 R 1 R 2 + -------------------- 1s R 1 C R1 ⋅⋅ + () 1s R 1 R 2 ⋅ R 1 R 2 + --------------------- C R1 ⋅⋅ + ⎝⎠ ⎛⎞ ----------------------------------------------------------------- ⋅ = f Z 1 2 π R 1 C R1 ⋅⋅ ⋅ ---------------------------------------------- = f P 1 2 π R 1 R 2 ⋅ R 1 R 2 + --------------------- C R1 ⋅⋅ ⋅ ------------------------------------------------------------- = f Z f P < Gs () G DIV s () G CO s () A 0 s () ⋅⋅ = |
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