L6718TR datasheet(53/71 Pages) STMICROELECTRONICS

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L6718

Output voltage positioning

The RSFB resistor can then be designed according to the RSLL, as follows:

Equation 7

8.5

Dynamic VID transition support

The L6718 manages dynamic VID transitions that allow the output voltage of both sections

to be modified during normal device operation for power management purposes.

When changing dynamically the regulated voltage (DVID), the system must charge or

discharge the output capacitor accordingly. This means that an extra-current IDVID needs to

be delivered (especially when increasing the output regulated voltage) and it must be

considered when setting the overcurrent threshold of both the sections. This current results:

Equation 8

where dVOUT / dTVID depends on the specific command issued (10 mV/μsec. for

SetVID_Fast and 2.5 mV/

μsec. for SetVID_Slow).

Overcoming the OC threshold during the dynamic VID causes the device to latch and

disable.

As soon as the controller receives a new valid command to set the VID level for one (or

both) of the two sections, the reference of the involved section steps up or down according

to the target-VID with the programmed slope until the new code is reached. If a new valid

command is issued during the transition, the device updates the target-VID level and

performs the dynamic transition up to the new code. Protection is increased during the

transition and re-activated with proper delay after the end of the transition to prevent false

triggering.

8.6

DVID optimization: REF/SREF

High slew rate for dynamic VID transitions cause overshoot and undershoot on the

regulated voltage, causing a violation of the microprocessor requirement. To compensate

this behavior and to remove any over/undershoot in the transition, each section features a

DVID optimization circuit.

The reference used for the regulation is available on the REF/SREF pins (see Figure 12).

Connect an RREF/CREF to GND (RSREF / CSREF for the single-phase) to optimize the DVID

behavior. Components may be designed as follows (multi-phase, same equations apply to

single-phase):

SFB

SLL

DCR

-------------

⋅

DVID

OUT

VID

------------------

⋅

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