LNBH25 datasheet(20/34 Pages) STMICROELECTRONICS

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I²C interface protocol

LNBH25

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Doc ID 022433 Rev 4

7.3

Data registers

The DATA 1..4 registers can be addressed both in write and read mode. In read mode they

return the last writing byte status received in the previous write transmission.

The following tables provide the Register Address values of Data 1..4 and a function

description of each bit.

N/A = Reserved bit.

All bits reset to “0” at power-on.

N/A = Reserved bit.

All bits reset to 0 at power-on.

Table 7.

DATA 1 (Read/Write register. Register address = 0X2)

BIT

Name

Value

Description

Bit 0

(LSB)

VSEL1

0/1

Output voltage selection bits. (Refer to

Table 14)

Bit 1

VSEL2

0/1

Bit 2

VSEL3

0/1

Bit 3

VSEL4

0/1

Bit 4

N/A

Reserved. Keep to "0"

Bit 5

N/A

Reserved. Keep to "0"

Bit 6

N/A

Reserved. Keep to "0"

Bit 7

(MSB)

N/A

Reserved. Keep to "0"

Table 8.

DATA 2 (Read/Write register. Register address = 0X3)

BIT

Name

Value

Description

Bit 0

(LSB)

TEN

22 kHz tone enabled. Tone output controlled by DSQIN pin

22 kHz tone output disabled

Bit 1

LPM

Low power mode activated (used only with 22 kHz tone output disabled)

Low power mode deactivated (keep always LPM = 0 during 22 kHz tone

transmission)

Bit 2

EXTM

DSQIN input pin is set to receive external 22 kHz TTL signal source

DSQIN input pin is set to receive external DiSEqC envelope TTL signal

Bit 3

N/A

Reserved. Keep to “0”

Bit 4

N/A

Reserved. Keep to "0"

Bit 5

N/A

Reserved. Keep to "0"

Bit 6

N/A

Reserved. Keep to "0"

Bit 7

(MSB)

N/A

Reserved. Keep to "0"

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