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LNBH25 데이터시트(PDF) 22 Page - STMicroelectronics

부품명 LNBH25
상세설명  Selectable output current limit by external resistor
PDF  34 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
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LNBH25 데이터시트(HTML) 22 Page - STMicroelectronics

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I²C interface protocol
LNBH25
22/34
Doc ID 022433 Rev 4
N/A = Reserved bit.
All bits reset to 0 at power-on.
7.4
Status registers
The STATUS 1, 2 registers can be addressed only in read mode and provide the diagnostic
functions described in the following tables.
N/A = Reserved bit.
All bits reset to 0 at power-on.
BIT
Name
Value
Description
Bit 6
THERM
1
If Thermal protection is activated (OTF=1), all VSEL 1..4 bits are reset to “0” and
LNB output (VOUT pin) is disabled. The VSEL bits must be set again by the master
after the overtemperature condition is removed (OTF=0).
0
In case of Thermal protection activation (OTF=1) the LNB output (VOUT pin) is
automatically enabled as soon as the overtemperature condition is removed
(OTF=0) with the previous VSEL bits setting.
Bit 7
(MSB)
COMP
1
DC-DC converter compensation set to use HIGH ESR capacitors (VUP pin)
0
DC-DC converter compensation set to use LOW ESR capacitors (VUP pin)
Table 10.
DATA 4 (Read/Write register. Register address = 0X5) (continued)
Table 11.
STATUS 1 (Read register. Register address = 0X0)
BIT
Name
Value
Description
Bit 0
(LSB)
OLF
1
VOUT pin overload protection has been triggered (IOUT > IMAX). Refer to Table 9 for
the overload operation settings (ISET, PCL, TIMER bits).
0
No overload protection has been triggered to the VOUT pin (IOUT < IMAX).
Bit 1
N/A
-
Reserved
Bit 2
VMON
1
Output voltage (VOUT pin) lower than VMON specification thresholds. Refer to
Table 17.
0
Output voltage (VOUT pin) is within the VMON specifications.
Bit 3
N/A
-
Reserved
Bit 4
PDO
1
Overcurrent detected on output pull-down stage for a time longer than the deglitch
period. This may happen due to an external voltage source present on the LNB
output (VOUT pin).
0
No overcurrent detected on output pull-down stage.
Bit 5
N/A
-
Reserved
Bit 6
OTF
1
Junction overtemperature is detected, TJ > 150 °C. See also THERM bit setting in
Table 10.
0
Junction overtemperature not detected, TJ < 135 °C. TJ is below thermal
protection threshold.
Bit 7
(MSB)
PNG
1
Input voltage (VCC pin) lower than LPD minimum thresholds. Refer to Table 13.
0
Input voltage (VCC pin) higher than LPD thresholds. Refer to Table 13.



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