ST7MC1K2 datasheet(91/371 Pages) STMICROELECTRONICS

91 / 371 page

Obsolete

Product(s)

- Obsolete

Product(s)

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto

On-chip peripherals

91/371

10.1.8

Using Halt mode with the watchdog (WDGHALT option)

If Halt mode is used when the watchdog is enabled, refresh the WDG counter before

executing the HALT instruction to avoid an unexpected WDG reset immediately after waking

up the microcontroller.

10.1.9

Watchdog interrupts

None.

10.1.10

Watchdog control register (WDGCR)

10.1.11

Watchdog window register (WDGWR)

WDGCR

Reset value: 0111 1111 (7Fh)

654

WDGA

T[6:0]

R/W

Table 35.

WDGCR register description

Bit

Name

Function

WDGA

Activation bit

This bit is set by software and only cleared by hardware after a reset. When

WDGA = 1, the watchdog can generate a reset.

0: Watchdog disabled

1: Watchdog enabled

Note: This bit is not used if the hardware watchdog option is enabled by option

byte.

6:0

T[6:0]

7-bit counter (MSB to LSB)

These bits contain the value of the watchdog counter. It is decremented every

16384 fOSC2 cycles (approx). A reset is produced when it rolls over from 40h to

3Fh (T6 becomes cleared).

WDGWR

Reset value: 0111 1111 (7Fh)

654

Reserved

W[6:0]

-R/W

Table 36.

WDGWR register description

Bit Name

Function

Reserved, must be kept cleared

6:0 W[6:0]

7-bit window value

These bits contain the window value to be compared to the downcounter.

Obsolete

Product(s)

- Obsolete

Product(s)

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