ST7MC1K2 datasheet(39/371 Pages) STMICROELECTRONICS

39 / 371 page

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Central processing unit

39/371

5.3.4

Condition code register (CC)

The 8-bit condition code register contains the interrupt masks and four flags representative

of the result of the instruction just executed. This register can also be handled by the push

and pop instructions.

These bits can be individually tested and/or controlled by specific instructions.

Reset value: 111x 1xxx

654

1I1

R/W

Table 5.

CC register description

Bit

Name

Function

5, 3

I1, I0

(interrupt)

Interrupt management bits

The combination of the I1 and I0 bits gives the current interrupt software

priority:

10: Interrupt software priority = level 0 (main)

01: Interrupt software priority = level 1

00: Interrupt software priority = level 2

11: Interrupt software priority = level 3 (interrupt disable)

These two bits are set/cleared by hardware when entering in interrupt. The

loaded value is given by the corresponding bits in the interrupt software

priority registers (IxSPR). They can be also set/cleared by software with the

RIM, SIM, IRET, HALT, WFI and push/pop instructions. See Section 7:

Interrupts on page 59 for more details.

(half carry)

Arithmetic management bit

This bit is set by hardware when a carry occurs between bits 3 and 4 of the

ALU during an ADD or ADC instructions. It is reset by hardware during the

same instructions.

0: No half carry has occurred

1: A half carry has occurred

This bit is tested using the JRH or JRNH instruction. The H bit is useful in

BCD arithmetic subroutines.

(negative)

Arithmetic management bit

This bit is set and cleared by hardware. It is representative of the result sign

of the last arithmetic, logical or data manipulation. It’s a copy of the result 7th

bit.

0: The result of the last operation is positive or null

1: The result of the last operation is negative (that is, the most significant bit

is a logic 1)

This bit is accessed by the JRMI and JRPL instructions.

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