ST7MC1K2 datasheet(151/371 Pages) STMICROELECTRONICS

151 / 371 page

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On-chip peripherals

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Even parity

The parity bit is calculated to obtain an even number of ‘1s’ inside the character made of the

7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.

Example: data = 00110101; 4 bits set

≥ parity bit is 0 if even parity is selected (PS bit = 0).

Odd parity

The parity bit is calculated to obtain an odd number of ‘1s’ inside the character made of the

7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.

Example: data = 00110101; 4 bits set

≥ parity bit is 1 if odd parity is selected (PS bit = 1).

Transmission mode

If the PCE bit is set then the MSB bit of the data written in the data register is not transmitted

but is changed by the parity bit.

Reception mode

If the PCE bit is set, the interface checks if the received data byte has an even number of

‘1s’ if even parity is selected (PS = 0) or an odd number of ‘1s’ if odd parity is selected

(PS = 1). If the parity check fails, the PE flag is set in the SCISR register and an interrupt is

generated if PCIE is set in the SCICR1 register.

10.5.6

Low power modes

10.5.7

Interrupts

The SCI interrupt events are connected to the same interrupt vector (see Section 7:

Interrupts).

Table 60.

Effect of low power modes on SCI

Mode

Description

Wait

No effect on SCI.

SCI interrupts cause the device to exit from Wait mode.

Halt

SCI registers are frozen.

In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited.

Table 61.

SCI interrupt control/wake-up capability

Interrupt event

Event

flag

Enable

control bit

Exit from

WAIT

Exit from

HALT

Transmit data register empty

TDRE

TIE

Yes

Transmission complete

TCIE

Received data ready to be read

RDRF

RIE

Overrun error or LIN synch error detected

OR/LHE

Idle line detected

IDLE

ILIE

Parity error

PIE

LIN header detection

LHDF

LHIE

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