ST7MC1K2 datasheet(252/371 Pages) STMICROELECTRONICS

252 / 371 page

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On-chip peripherals

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto

252/371

Figure 117. Complementary PWM signals with chopping frequency on high and low side drivers

10.6.10

PWM generator block

The PWM generator block produces three independent PWM signals based on a single carrier frequency

with individually adjustable duty cycles.

Depending on the motor driving method, one or three of these signals may be redirected to the other

functional blocks of the motor control peripheral, using the PCN bit in the MDTG register.

When driving PM BLDC motors in six-step mode (voltage mode only, either sensored or sensorless) a

single PWM signal (phase U) is used to supply the input stage, PWM and channel manager blocks

according to the selected modes.

For other kind of motors requiring independent PWM control for each of the three phases, all PWM

signals (phases U, V and W) are directed to the channel manager, in which deadtime or a high frequency

carrier may be added. This is the case of AC induction motors or PMAC motors for instance, supplied

with 120° shifted sinewaves in voltage mode.

Main features

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12-bit PWM free-running up/down counter with up to 16 MHz input clock (Fmtc)

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Edge-aligned and center-aligned PWM operating modes

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Possibility to reload compare registers twice per PWM period in center-aligned mode

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Full-scale PWM generation

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PWM update interrupt generation

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8-bit repetition counter

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8-bit PWM mode

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Timer resynchronization feature

Reference input signal

Output A

Output B

Delay

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ST7MC1K2 데이터시트(PDF) 252 Page - STMicroelectronics

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