ST72321R7-Auto datasheet(68/243 Pages) STMICROELECTRONICS

68 / 243 page

Power saving modes

ST72321xx-Auto

68/243

Doc ID 13829 Rev 1

Figure 28.

Halt mode flowchart

WDGHALT is an option bit. See Section 21.1.1: Flash configuration on page 223 for more details.

Peripheral clocked with an external clock source can still be active.

Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to

Table 20: Interrupt mapping for more details.

Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are

set to the current software priority level of the interrupt routine and recovered when the CC register is

popped.

HALT INSTRUCTION

RESET

INTERRUPT (3)

CPU

OSCILLATOR

PERIPHERALS (2)

I[1:0] BITS

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

OFF

XX (4)

CPU

OSCILLATOR

PERIPHERALS

I[1:0] BITS

XX (4)

256 OR 4096 CPU CLOCK

DELAY

WATCHDOG

ENABLE

DISABLE

WDGHALT (1)

WATCHDOG

RESET

(MCCSR.OIE = 0)

CYCLE

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