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ST72321R7-Auto 데이터시트(PDF) 44 Page - STMicroelectronics |
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ST72321R7-Auto 데이터시트(HTML) 44 Page - STMicroelectronics |
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44 / 243 page ![]() Supply, reset and clock management ST72321xx-Auto 44/243 Doc ID 13829 Rev 1 Figure 14. Low voltage detector versus reset 6.6.2 Auxiliary voltage detector (AVD) The auxiliary voltage detector function (AVD) is based on an analog comparison between a VIT-(AVD) and VIT+(AVD) reference value and the VDD main supply or the external EVD pin voltage level (VEVD). The VIT- reference value for falling voltage is lower than the VIT+ reference value for rising voltage in order to avoid parasitic detection (hysteresis). The output of the AVD comparator can be read directly by the application software through a real-time status bit (AVDF) in the SICSR register. This bit is read only. Caution: The AVD function is active only if the LVD is enabled through the option byte. Monitoring the VDD main supply This mode is selected by clearing the AVDS bit in the SICSR register. The AVD voltage threshold value is relative to the selected LVD threshold configured by option byte (see Section 21.1.1: Flash configuration on page 223). If the AVD interrupt is enabled, an interrupt is generated when the voltage crosses the VIT+(AVD) or VIT-(AVD) threshold (AVDF bit toggles). In the case of a drop in voltage, the AVD interrupt acts as an early warning, allowing software to shut down safely before the LVD resets the microcontroller. See Figure 15. The interrupt on the rising edge is used to inform the application that the VDD warning state is over. If the voltage rise time trv is less than 256 or 4096 CPU cycles (depending on the reset delay selected by option byte), no AVD interrupt will be generated when VIT+(AVD) is reached. If trv is greater than 256 or 4096 cycles ● two AVD interrupts will be received if the AVD interrupt is enabled before the VIT+(AVD) threshold is reached: the first when the AVDIE bit is set, and the second when the threshold is reached. ● only one AVD interrupt will occur if the AVD interrupt is enabled after the VIT+(AVD) threshold is reached. VDD VIT+ RESET VIT- Vhys |
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