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ST72321R7-Auto 데이터시트(PDF) 157 Page - STMicroelectronics

부품명 ST72321R7-Auto
상세설명  PLL for 2x frequency multiplication
PDF  243 Pages
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ST72321R7-Auto 데이터시트(HTML) 157 Page - STMicroelectronics

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ST72321xx-Auto
I2C bus interface (I2C)
Doc ID 13829 Rev 1
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16.3.3
SDA/SCL line control
Transmitter mode
The interface holds the clock line low before transmission to wait for the microcontroller to
write the byte in the data register.
Receiver mode
The interface holds the clock line low after reception to wait for the microcontroller to read
the byte in the data register.
The SCL frequency (fSCL) is controlled by a programmable clock divider which depends on
the I2C bus mode.
When the I2C cell is enabled, the SDA and SCL ports must be configured as floating inputs.
In this case, the value of the external pull-up resistor used depends on the application.
When the I2C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins.
Figure 67.
I2C interface block diagram
DATA REGISTER (DR)
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER 1 (OAR1)
CLOCK CONTROL REGISTER (CCR)
STATUS REGISTER 1 (SR1)
CONTROL REGISTER (CR)
CONTROL LOGIC
STATUS REGISTER 2 (SR2)
INTERRUPT
CLOCK CONTROL
DATA CONTROL
SCL or SCLI
SDA or SDAI
OWN ADDRESS REGISTER 2 (OAR2)



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