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ST72321R7-Auto 데이터시트(PDF) 209 Page - STMicroelectronics

부품명 ST72321R7-Auto
상세설명  PLL for 2x frequency multiplication
PDF  243 Pages
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ST72321R7-Auto 데이터시트(HTML) 209 Page - STMicroelectronics

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ST72321xx-Auto
Electrical characteristics
Doc ID 13829 Rev 1
209/243
Figure 91.
RESET pin
protection when LVD is disabled
Note:
The reset network protects the device against parasitic resets.
The output of the external reset circuit must have an open-drain output to drive the ST7
reset pad. Otherwise the device can be damaged when the ST7 generates an internal reset
(LVD or watchdog).
Whether the reset source is internal or external, the user must ensure that the level on the
RESET pin can go below the VIL maximum level specified in Section 19.9.1 on page 207.
Otherwise the reset will not be taken into account internally.
Because the reset circuit is designed to allow the internal RESET to be output in the RESET
pin, the user must ensure that the current sunk on the RESET pin is less than the absolute
maximum value specified for IINJ(RESET) in Section 19.2.2 on page 187.
19.9.2
ICCSEL/VPP pin
Subject to general operating conditions for VDD, fCPU, and TA unless otherwise specified.
0.01µF
EXTERNAL
RESET
CIRCUIT
USER
Required
ST72XXX
PULSE
GENERATOR
Filter
RON
VDD
WATCHDOG
INTERNAL
RESET
Table 129.
ICCSEL/VPP pin characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
VIL
Input low level voltage(1)
1.
Data based on design simulation and/or technology characteristics, not tested in production.
Flash versions
VSS
0.2
V
ROM versions
VSS
0.3xVDD
VIH
Input high level voltage(1)
Flash versions
VDD-0.1
12.6
ROM versions
0.7xVDD
VDD
IL
Input leakage current
VIN =VSS
±1
µA



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