ST72321R7-Auto datasheet(235/243 Pages) STMICROELECTRONICS

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ST72321xx-Auto

Known limitations

Doc ID 13829 Rev 1

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To avoid this, a semaphore is set to ‘1’ before checking the level change. The semaphore is

changed to level '0' inside the interrupt routine. When a level change is detected, the

semaphore status is checked. If it is ‘1’, it means that the last interrupt has been missed. In

this case, the interrupt routine is invoked with the call instruction.

There is another possible case, that is, if PxOR or PxDDR are written to with global

interrupts disabled (interrupt mask bit set). In this case, the semaphore is changed to ‘1’

when the level change is detected. Detecting a missed interrupt is done after the global

interrupts are enabled (interrupt mask bit reset) and by checking the status of the

semaphore. If it is ‘1’, it means that the last interrupt was missed and the interrupt routine is

invoked with the call instruction.

To implement the workaround, the following software sequence is to be followed for writing

into the PxOR/PxDDR registers. The example is for Port PF1 with falling edge interrupt

sensitivity. The software sequence is given for both cases (global interrupts disabled / global

interrupts enabled):

Case 1: Writing to PxOR or PxDDR with global interrupts enabled:

LD A,#01

LD sema,A

; set the semaphore to '1'

LD A,PFDR

AND A,#02

X,A

; store the level before writing to PxOR/PxDDR

LD A,#$90

LD PFDDR,A

; Write to PFDDR

LD A,#$ff

PFOR,A

; Write to PFOR

LD A,PFDR

AND A,#02

LD Y,A

; store the level after writing to PxOR/PxDDR

LD A,X

; check for falling edge

cp A,#02

jrne OUT

TNZ Y

jrne OUT

LD A,sema

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