ST72344S4 datasheet(48/247 Pages) STMICROELECTRONICS

48 / 247 page

Supply, reset and clock management

ST72344xx, ST2345xx

48/247

Doc ID 12321 Rev 6

7.5.4

Internal low-voltage detector (LVD) reset

Two different reset sequences caused by the internal LVD circuitry can be distinguished:

●

Power-on reset

●

Voltage-drop reset

The device RESET pin acts as an output that is pulled low when VDD<VIT+ (rising edge) or

VDD<VIT- (falling edge) as shown in Figure 17.

The LVD filters spikes on VDD larger than tg(VDD) to avoid parasitic resets.

Note:

It is recommended to make sure that the VDD supply voltage rises monotonously when the

device is exiting from Reset, to ensure the application functions properly.

7.5.5

Internal watchdog reset

The reset sequence generated by a internal Watchdog counter overflow is shown in

Figure 17.

Starting from the Watchdog counter underflow, the device RESET pin acts as an output that

is pulled low during at least tw(RSTL)out.

Figure 17.

Reset sequences

7.6

System integrity management (SI)

The system integrity management block contains the low-voltage detector (LVD) and

auxiliary-voltage detector (AVD) functions. It is managed by the SICSR register.

Note:

A reset can also be triggered following the detection of an illegal opcode or prebyte code.

Refer to Section 12.2.1: Illegal opcode reset for further details.

VDD

Run

RESET PIN

EXTERNAL

WATCHDOG

ACTIVE PHASE

VIT+(LVD)

VIT-(LVD)

th(RSTL)in

tw(RSTL)out

Run

th(RSTL)in

ACTIVE

WATCHDOG UNDERFLOW

tw(RSTL)out

Run

RESET

SOURCE

SHORT EXT.

RESET

LVD

RESET

LONG EXT.

RESET

WATCHDOG

RESET

INTERNAL RESET (256 or 4096 TCPU)

VECTOR FETCH

tw(RSTL)out

PHASE

ACTIVE

PHASE

ACTIVE

PHASE

DELAY

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