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STM8S005C6 데이터시트(PDF) 54 Page - STMicroelectronics

부품명 STM8S005C6
상세설명  Extended instruction set
PDF  97 Pages
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Electrical characteristics
STM8S005C6 STM8S005K6
54/97
DocID022186 Rev 4
Total current consumption and timing in forced reset state
Current consumption of on-chip peripherals
Subject to general operating conditions for VDD and TA.
HSI internal RC/fCPU = fMASTER = 16 MHz.
Table 28. Total current consumption and timing in forced reset state
Symbol
Parameter
Conditions
Typ
Max(1)
Unit
IDD(R)
Supply current in reset state (2)
VDD = 5 V
500
-
µA
VDD = 3.3 V
400
-
tRESETBL
Reset release to bootloader vector
fetch
--
150
µs
1.
Data guaranteed by design, not tested in production.
2.
Characterized with all I/Os tied to VSS.
Table 29. Peripheral current consumption
Symbol
Parameter
Typ.
Unit
IDD(TIM1)
TIM1 supply current (1)
1.
Data based on a differential IDD measurement between reset configuration and timer counter running at 
16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.
230
µA
IDD(TIM2)
TIM2 supply current (1)
115
IDD(TIM3)
TIM3 timer supply current (1)
90
IDD(TIM4)
TIM4 timer supply current (1)
30
IDD(UART2)
UART2 supply current (2)
2.
Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and
not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. Not
tested in production.
110
IDD(SPI)
SPI supply current (2)
45
IDD(I2C)
I2C supply current (2)
65
IDD(ADC1)
ADC1 supply current when converting (3)
3.
Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions. Not tested in production.
955



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