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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STM8S105C4 데이터시트(PDF) 79 Page - STMicroelectronics |
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STM8S105C4 데이터시트(HTML) 79 Page - STMicroelectronics |
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79 / 121 page  DocID14771 Rev 15 79/121 STM8S105x4/6 Electrical characteristics 90 Figure 38. Typical NRST pull-up resistance RPU vs VDD @ 4 temperatures Figure 39. Typical NRST pull-up current Ipu vs VDD @ 4 temperatures The reset network shown in Figure 40 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below VIL(NRST) max (see Table 41: NRST pin characteristics ), otherwise the reset is not taken into account internally. For power consumption sensitive applications, the external reset capacitor value can be reduced to limit the charge/discharge current. If NRST signal is used to reset external circuitry, attention must be taken to the charge/discharge time of the external capacitor to fulfill the external devices reset timing conditions. Minimum recommended capacity is 100 nF. |
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