STM8S105C4 datasheet(29/121 Pages) STMICROELECTRONICS

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STM8S105x4/6

Pinout and pin description

PE0/ CLK_CCO

I/O

HS O3

Port E0

Configura

ble clock

output

PD0/

TIM3_CH2

[TIM1_BKIN]

[CLK_CCO]

I/O

HS O3

Port D0

Timer 3 -

channel 2

TIM1_BK

[AFR3]/

CLK_CC

O [AFR2]

PD1/ SWIM(5)

I/O

HS O4

Port D1

SWIM

data

interface

PD2/

TIM3_CH1

[TIM2_CH3]

I/O

HS O3

Port D2

Timer 3 -

channel 1

TIM2_CH

3 [AFR1]

PD3/

TIM2_CH2

[ADC_ETR]

I/O

HS O3

Port D3

Timer 2 -

channel 2

ADC_ET

R [AFR0]

PD4/

TIM2_CH1

[BEEP]

I/O

HS O3

Port D4

Timer 2 -

channel 1

BEEP

output

[AFR7]

PD5/

UART2_TX

I/O

Port D5

UART2

data

transmit

PD6/

UART2_RX

I/O

Port D6

UART2

data

receive

PD7/ TLI

[TIM1_CH4

I/O

Port D7

Top level

interrupt

TIM1_CH

4 [AFR4]

1. A pull-up is applied to PF4 during the reset phase. This pin is input floating after reset release.

AIN12 is not selectable in ADC scan mode or with analog watchdog.

3. In 44-pin package, AIN9 cannot be used by ADC scan mode.

4. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD are

not implemented).

5. The PD1 pin is in input pull-up during the reset phase and after internal reset release.

Table 5. STM8S105x4/6 pin description (continued)

Pin number

Pin name

Type

Input

Output

Main

function

(after

reset)

Default

alternate

function

Alternate

function

after

remap

[option

bit]

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