STM8S105C4 datasheet(21/121 Pages) STMICROELECTRONICS

21 / 121 page

DocID14771 Rev 15

21/121

STM8S105x4/6

Product overview

LIN slave mode



Autonomous header handling - one single interrupt per valid message header



Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15%



Synch delimiter checking



11-bit LIN synch break detection - break detection always active



Parity check on the LIN identifier field



LIN error management



Hot plugging support

4.14.2

SPI



Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave



Full duplex synchronous transfers



Simplex synchronous transfers on two lines with a possible bidirectional data line



Master or slave operation - selectable by hardware or software



CRC calculation



1 byte Tx and Rx buffer



Slave/master selection input pin

4.14.3

I2C



I²C master features:

–

Clock generation

–

Start and stop generation



I²C slave features:

–

Programmable I2C address detection

–

Stop bit detection



Generation and detection of 7-bit/10-bit addressing and general call



Supports different communication speeds:

–

Standard speed (up to 100 kHz)

–

Fast speed (up to 400 kHz)

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