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DS2148 데이터시트(PDF) 70 Page - Dallas Semiconductor |
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DS2148 데이터시트(HTML) 70 Page - Dallas Semiconductor |
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70 / 75 page ![]() DS2148/Q48 70 of 75 AC CHARACTERISTICS—RECEIVE SIDE (-40 °C to +85°C; VDD = 5.0V ± 5%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES RCLK Period tCP 488 648 ns ns 1 2 RCLK Pulse Width tCH tCL 200 200 ns ns 3 3 RCLK Pulse Width tCH tCL 150 150 ns ns 4 4 Delay RCLK to RPOS, RNEG, PBEO, RBPV Valid tDD 50 ns NOTES: 1) E1 Mode. 2) T1 or J1 Mode. 3) Jitter attenuator enabled in the receive path. 4) Jitter attenuator disabled or enabled in the transmit path. RECEIVE SIDE TIMING Figure 12-9 NOTES: 1) RCES = 1 (CCR2.0) or CES = 1. 2) RCES = 0 (CCR2.0) or CES = 0. 3) RNEG is in NRZ mode (CCR1.6 = 1). tDD RPOS, RNEG RCLK2 CL t tCP CH t RCLK1 PBEO tDD bit error BPV/ EXZ/ CV PRBS Detector Out of Sync RNEG3 BPV/ EXZ/ CV |
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