DS2148 datasheet(44/75 Pages) DALLAS

44 / 75 page

DS2148/Q48

44 of 75

RDNCD2 (10H): RECEIVE DOWN CODE DEFINITION REGISTER 2

(MSB)

(LSB)

C15

C14

C13

C12

C11

C10

SYMBOL

POSITION

DESCRIPTION

C15

RDNCD2.7

Receive Down Code Definition Bit 15

C14

RDNCD2.6

Receive Down Code Definition Bit 14

C13

RDNCD2.5

Receive Down Code Definition Bit 13

C12

RDNCD2.4

Receive Down Code Definition Bit 12

C11

RDNCD2.3

Receive Down Code Definition Bit 11

C10

RDNCD2.2

Receive Down Code Definition Bit 10

RDNCD2.1

Receive Down Code Definition Bit 9

RDNCD2.0

Receive Down Code Definition Bit 8

8.2

Loopbacks

8.2.1 Remote Loopback (RLB)

When RLB (CCR6.6) is enabled, the DS2148 is placed into remote loopback. In this loopback, data from

the clock/data recovery state machine will be looped back to the transmit path passing through the jitter

attenuator if it is enabled. The data at the RPOS and RNEG pins will be valid while data presented at

TPOS and TNEG will be ignored (Figure 3-1).

If the Automatic Remote Loop Back Enable (CCR6.5) is set to a one, the DS2148 will automatically go

into remote loop back when it detects the loop up code programmed in the Receive Up Code Definition

Registers (RUPCD1 and RUPCD2) for a minimum of 5 seconds. When the DS2148 detects the loop

down code programmed in the Receive Loop Down Code Definition registers (RDNCD1 and RDNCD2)

for a minimum of 5 seconds, the DS2148 will come out of remote loop back. Setting ARLBE to a zero

also can disable the ARLB.

8.2.2 Local Loopback (LLB)

When LLB (CCR6.7) is set to a one, the DS2148 is placed into local loopback. In this loopback, data on

the transmit-side will continue to be transmitted as normal. TCLK and TPOS/TNEG will pass through the

jitter attenuator (if enabled) and be output at RCLK and RPOS/RNEG. Incoming data from the line at

RTIP and RRING will be ignored. If Transmit Unframed All Ones (CCR3.7) is set to a one while in LLB,

TTIP and TRING will transmit all ones while TCLK and TPOS/TNEG will be looped back to RCLK and

RPOS/RNEG (Figure 3-1).

DS2148 데이터시트(PDF) 44 Page - Dallas Semiconductor

DS2148 데이터시트(HTML) 44 Page - Dallas Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

데이터시트 다운로드

링크 URL