STA311B datasheet(14/102 Pages) STMICROELECTRONICS

14 / 102 page

Device overview

STA311B

14/102

DocID024340 Rev 1

Phase-locked loop (PLL)

The phase-locked loop section provides the system timing signals and CKOUT.

Clock output (CKOUT)

System synchronization and master clocks are provided by CKOUT.

PWM outputs (OUT1 through OUT8)

The PWM outputs provide the input signal for the power devices.

External amplifier power-down (EAPD)

This signal can be used to control the power-down of the FFX power devices.

Serial data out (SDO_12, SDO_34, SDO_56, SDO_78)

When the pop-noise removal feature is disabled, these are the outputs for the audio

information. Six different formats are available including I²S, left-or right-justified, LSB or

MSB first, with word widths of 16, 18, 20 and 24 bits.

However, when the pop-noise removal feature is enabled, SDO_12 and SDO_34 output the

audio information, whereas SDO_56 is used as the external power bridge fault input and

SDO_78 as the external power bridge tristate signal.

Device power-down (PWDN)

Pulling PWDN low begins the power-down sequence which puts the STA311B into a

low-power state. EAPD goes low approximately 30 ms later.

Frequency sampling autodetection

The system clock is generated by PLL using XTI or BICKI input, and the ratio (IR) between

the frequency sampling (Fs) of the audio serial and the PLL clock has to be set in the

appropriate registers via the I²C interface. If the Fs autodetection function has been

enabled, the IR parameter will be set automatically based on the Fs input (see Fs

autodetection on page 32).

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