STA311B datasheet(31/102 Pages) STMICROELECTRONICS

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STA311B

Registers

102

8.2

8.2.1

Configuration register A (0x00)

The STA311B supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,

176.4 kHz, 192 kHz, 2.8224 MHz DSD. Therefore the internal clocks are:



65.536 MHz for 32 kHz



90.3168 MHz for 44.1 kHz, 88.2 kHz, 176.4 kHz, and DSD



98.304 MHz for 48 kHz, 96 kHz, 192 kHz

The external clock frequency provided to the XTI or BICKI pin (depending on the MCS

settings) must be a multiple of the input sampling frequency (fs). The relationship between

the input clock (either XTI or BICKI) and the input sampling rate is determined by both the

MCS[2:0] and the IR[1:0] (input rate) register bits in normal mode, if the Fs autodetect mode

has been set, the IR[1:0] parameter and the BST32K bit will be set automatically (see Fs

autodetection on page 32). The MCS[2:0] bits determine the PLL factor generating the

internal clock and the IR[1:0] bits determine the oversampling ratio used internally.

If XTI input is not used, related pin must be tied to GND.

To get 98.304 MHz of system clock frequency when fs = 32 kHz, an extra oversampling

factor is available by setting the BST32K bit in the 0x75 register (see Clock manager

configuration register (0x75) on page 93).

COS1

COS0

DSPB

IR1

IR0

MCS2

MCS1

MCS0

000

Bit

RST

Name

Description

0RW

MCS0

Master clock select: selects the ratio between the

input I²S sampling frequency and the input clock.

1RW

MCS1

2RW

MCS2

Input sampling rate

fs (kHz)

MCS[2:0]

BICKI

XTI

111

110

10-

011

010

001

000

32, 44.1, 48

64*fs

128*fs

256*fs

384*fs

512*fs

768*fs

88.2, 96

64*fs

32*fs

64*fs

128*fs

192*fs

256*fs

384*fs

176.4, 192

64*fs

32*fs

64*fs

128*fs

192*fs

256*fs

DSD/PDM

2*fs

4*fs

6*fs

8*fs

12*fs

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