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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STA321MPL1 데이터시트(PDF) 18 Page - STMicroelectronics |
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STA321MPL1 데이터시트(HTML) 18 Page - STMicroelectronics |
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18 / 80 page  I2C bus operation STA321MPL1 18/80 DocID029389 Rev 1 The 8th bit (LSB) identifies a read or write operation RW. This bit is set to 1 in read mode and 0 for write mode. After a START condition, the STA321MPL1 identifies the device address on the bus and if a match is found, it acknowledges the identification on the SDA bus during the 9th-bit time. The byte following the device identification byte is the internal space address. 4.3 Write operation Following a START condition, the master sends a device select code with the RW bit set to 0. The STA321MPL1 acknowledges this and the writes for the byte of the internal address. After receiving the internal byte address, the STA321MPL1 responds again with an acknowledgement. 4.3.1 Byte write In byte write mode, the master sends one data byte, this is acknowledged by the Omega FFX core. The master then terminates the transfer by generating a STOP condition. 4.3.2 Multi-byte write The multi-byte write modes can start from any internal address. The master generating a STOP condition terminates the transfer. Figure 6. Write mode sequence |
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