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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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STA321MPL1 데이터시트(PDF) 28 Page - STMicroelectronics |
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STA321MPL1 데이터시트(HTML) 28 Page - STMicroelectronics |
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28 / 80 page  Registers STA321MPL1 28/80 DocID029389 Rev 1 5.2.3 Configuration register D (0x03) The FFX power output mode selects how the FFX output timing is configured. Different power devices use different output modes. D7 D6 D5 D4 D3 D2 D1 D0 MPC CSZ4 CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0 11 111 11 0 Bit RW RST Name Description 0RW 0 OM0 FFX power output mode: selects configuration of FFX output 1RW 1 OM1 Bit RW RST Name Description 2RW 1 CSZ0 Contra size register: when OM[1,0] = 11, this register determines the size of the FFX compensating pulse from 0 clock ticks to 31 clock periods 3RW 1 CSZ1 4RW 1 CSZ2 5RW 1 CSZ3 6RW 1 CSZ4 CSZ[4:0] Compensating pulse size 00000 0 clock period compensating pulse size 00001 1 clock period compensating pulse size …… 11111 31 clock period compensating pulse size |
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