A8603KESTR-R datasheet(33/42 Pages) ALLEGRO

33 / 42 page

Multiple-Output Regulator for

Automotive LCD Displays

A8603

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

THERMAL ANALYSIS

The thermal resistance, RθJA, of the QFN-24 thermally enhanced

package is 37°C/W. For long-term reliability, the package junc-

tion temperature should be kept at 150°C or below. Assuming a

maximum ambient temperature of 85°C, the power dissipation

budget, PD(max), is:

PD(max) = (TJ(max) – TA(max))/RθJA

= (150 (°C) – 85 (°C)) / 37 (°C/W) = 1.75 W

The power losses of the IC come from two main contributors: the

boost stage and the output regulators. These losses are calculated

separately, and then summed as follows.

Boost Stage Power Loss

To estimate the dissipation of the boost stage, calculate and sum

the losses due to switching losses, PSW, and conduction losses in

the switch, PCOND:

PD(BOOST) = PCOND + PSW

As an example, consider the following load conditions:

AVDD

VCOM

VGL

VGH

Boost

Voltage (V)

-8

12.1

Max. Current (mA)

100

110

1. Estimate the maximum output power for boost stage:

POUT(max) = VOUT(max) × IOUT (max)

IOUT = IAVDD + IVCOM + IVGL + 2 × IVGH

Based on the above load conditions, we conclude that Boost

VOUT = 12.1 V (see “Boost Controller” section for explanation)

and IOUT = 110 mA. Therefore POUT(max) = 12.1 V × 0.11 A =

1.33 W

2. Estimate the maximum input current:

IIN = PIN /VIN

PIN = POUT /η

where η is efficiency.

Assume minimum VIN of 3 V and a conservative efficiency

of 80%:

IIN = (1.33 W/0.8)/3 V = 0.55 A.

3. Estimate conduction loss for the internal switch:

PCOND = (IIN)2 × RDS(on) × D

D = 1 – VIN /(VOUT + VD)

where D = Duty Cycle of boost switch, VD is the forward

voltage drop of the external boost diode.

Substitute minimum VIN = 3 V, VOUT = 12.1 V, VD = 0.4 V to

get D = 0.76.

PCOND = (0.55 A)2 × 0.7 Ω × 0.76 = 0.16 W

Note that RDS(on) is 0.5 Ω typical, plus 40% for temperature

compensation at 125°C.

4. Estimate switching loss for the internal boost switch:

PSW = ISW × VSW × (tr + tf ) × fSW /2

Where ISW = IIN approximately, VSW = VOUT + VD; tr is the

rise time, and tf the fall time, of VSW.

Assume tr = tf = 10 ns,

PSW = 0.55 A × 12.5 V × (10 ns + 10 ns) × 2 MHz/2 = 0.14 W

Therefore the total power dissipation on the boost stage is:

PD(BOOST) = PCOND + PSW = 0.30 W

Output Regulator Power Loss

The output regulator power dissipation is the sum of the indi-

vidual linear regulators:

PD(REG) = PLDO1 + PLDO2 + PLDO3 + PLDO4

Where LDO1-4 are linear regulators for AVDD, VCOM, VGL

and VGH, respectively.

PLDO1 = (VOUT – VAVDD) × ( IAVDD + IVCOM )

PLDO2 = (VAVDD – VVCOM) × IVCOM

PLDO3 = (VOUT – |VVGL|) × IVGL

PLDO4 = (VOUT – VVGH/2) × 2 × IVGH

Using the previously stated operating conditions, we then have:

PLDO1 = (12.1 V – 10 V) x 104 mA = 218 mW)

PLDO2 = (10 V – 4 V) × 4 mA = 24 mW

PLDO3 = (12.1 V – 8 V) × 2 mA = 8 mW

PLDO4 = (12.1 V – 18 V/2) × 2 × 2 mA = 12 mW

Finally, the IC consumes a bias current of approximately 5 mA

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