A8603KESTR-R datasheet(42/42 Pages) ALLEGRO

42 / 42 page

Multiple-Output Regulator

for Automotive LCD Displays

A8603

A-5

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

I2C-Compatible Interface Timing Diagram

tSU:STA tHD:STA

tSU:DAT

tHD:DAT

tBUF

tSU:STO

tHIGH

tLOW

SDA

SCL

I2C-Compatible Timing Requirements

Characteristics

Symbol

Min.

Typ.

Max.

Units

Bus Free Time Between Stop/Start

tBUF

1.3

–

μs

Hold Time Start Condition

tHD:STA

0.6

–

μs

Setup Time for Start Condition

tSU:STA

0.6

–

μs

SCL Low Time

tLOW

1.3

–

μs

SCL High Time

tHIGH

0.6

–

μs

Data Setup Time

tSU:DAT

100

–

Data Hold Time*

tHD:DAT

–

900

Setup Time for Stop Condition

tSU:STO

0.6

–

μs

Output Fall Time from VSCL(H) to VSCL(L)

tOF

–

250

*For tHD:DAT(min), the master device must provide a hold time of at least 300 ns for the SDA

signal in order to bridge the undefined region of the SCL signal falling edge.

1. Start

2. SDA can change state only when SCL = low

3. SDA must be stable before SCL goes high

4, 5. SCL and SDA output fall time < 250 ns

6. Stop

7. Restart

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