CS43130 datasheet(22/137 Pages) CIRRUS

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DS1073F1

CS43130

3 Characteristics and Specifications

3.I2S interface timing

4.TDM interface timing

(shown with xSP_FSD = 010, xSP_LCHI = 1)

5.Applies to Master and Slave Modes, unless specified otherwise.

6.Maximum LRCK duty cycle is equal to frame length, in SCLK periods, minus 1. Maximum duty cycle occurs when LRCK high (xSP_LCHI) is set to

768 SCLK periods and LRCK period (xSP_LCPR) is set to 769 SCLK periods.

7.Data may be latched/launched on either the rising or falling edge of SCLK.

8.SCLK duty cycle in Master Mode depends on Master Mode clock configuration, and can vary by up to 1 MCLKEXT period.

9.Data is latched/launched on the rising or falling edge of SCLK as determined by xSP_SCPOL_OUT, xSP_SCPOL_IN, and xSP_FSD bits. See the

SCLK launching specs in Table 3-18.

Table 3-19. DSD Switching Characteristic

Test conditions (unless specified otherwise): Fig. 2-1 shows CS43130 connections; GNDA = GNDCP = GNDD = 0 V; voltages are with respect to ground;

parameters can vary with VL; typical performance data taken with VL = VD = VA = VCP = 1.8 V, VP = 3.6 V; min/max performance data taken with VL =

1.8 V; VD = VA = VCP = 1.8 V, VP = 3.6 V; TA = +25°C; CL = 60 pF; Logic 0 = ground, Logic 1 = VL; output timings are measured at VOL and VOH

thresholds (see Table 3-11).

Parameter 1,2

1.Serial audio input interface timing

2.Phase modulation mode serial audio input interface timing

Symbol

Minimum

Typical

Maximum

Units

DSDCLK duty cycle

—

DSDCLK pulse width low

tSCLKL

—

DSDCLK pulse width high

tSCLKH

—

DSDCLK frequency

(64× oversampled)

(128× oversampled)

—

1.024

2.048

2.8224

5.6448

fMCLK_INT/8

fMCLK_INT/4

MHz

DSDA/DSDB valid to DSDCLK rising setup time

tSDLRS

—

DSDCLK rising to DSDA or DSDB hold time

tSDH

—

DSD clock to data transition (Phase Modulation Mode)

tDPM

–20

—

SCLK

(CPOL = 1)

SDIN

tSU:SDI

tH:SDI

LRCK/FSYNC

tD:CLK–FSYNC

1/Fs

...

fSCLK = N · Fs

tSU:FSYNC

tH:FSYNC

tLO:SCLK

tHI:SCLK

SCLK

(CPOL = 0)

...

1/fSCLK

...

SCLK

SDIN

tSU:SDI

tH:SDI

LRCK/FSYNC

tD:CLK-FSYNC

1/fSCLK

Don’t Care

Frame location 0

Frame location N -1

1/Fs

...

fSCLK = N · Fs

tSU :FSYNC

tH:FSYNC

tHI:FSYNC

tLO:SCLK

tHI:SCLK

DSDCLK

DSDA,

DSDB

tSDLRS

tSDH

tSCLKL

tSCLKH

DSDCLK

(128

•Fs)

DSDCLK

(64

•Fs)

DSDA,

DSDB

tDPM

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