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WM8803CDT/V 데이터시트(PDF) 15 Page - Wolfson Microelectronics plc

부품명 WM8803CDT/V
상세설명  DIGITAL AUDIO INTERFACE RECEIVER
PDF  45 Pages
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제조업체  WOLFSON [Wolfson Microelectronics plc]
홈페이지  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8803CDT/V 데이터시트(HTML) 15 Page - Wolfson Microelectronics plc

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WM8803
w
PP Rev 1.1 September 2003
15
PLLCK1
PLLCK0
XISEL1
XISEL0
CLKOUT
BCLK
LRCLK
0
0
0
0
22.5792MHz
5.6448MHz
88.2kHz
0
0
0
1
24.5760MHz
6.1440MHz
96kHz
0
0
1
0
33.8688MHz
8.4672MHz
132.3kHz
0
1
0
0
22.5792MHz
3.7632MHz
58.8kHz
0
1
0
1
24.5760MHz
4.0960MHz
64kHz
0
1
1
0
33.8688MHz
5.6448MHz
88.2kHz
1
0
0
0
22.5792MHz
5.6448MHz
88.2kHz
1
0
0
1
24.5760MHz
6.1440MHz
96kHz
1
0
1
0
33.8688MHz
8.4672MHz
132.3kHz
1
1
0
0
22.5792MHz
5.6448MHz
88.2kHz
1
1
0
1
24.5760MHz
6.1440MHz
96kHz
1
1
1
0
33.8688MHz
8.4672MHz
132.3kHz
Table 7 XIN Clock Source Mode Output Clocks
Note:
1.
XISEL2 = 1, PLL unlocked state or forced setting
PLLCK1
PLLCK0
CLKOUT
BCLK
LRCLK
0
0
256 s
64fs
Fs
0
1
384fs
64fs
Fs
1
0
512fs
64fs
Fs
1
1
256fs
64fs
Fs
Table 8 PLL Clock Source Mode Output Clocks (PLL Locked State)
The CLKOUT output clock frequency can be set to 1/2 its normal value by MCKHFO, regardless of
the PLL locked/unlocked state. Clock switching using MCKHFO can also be performed in the PLL
locked state without losing that locked state, but clock continuity is not maintained.
If the audio output format is set to bi-phase data output, the BCLK output clock frequency will be
doubled to 128fs when the PLL circuit is locked. However, when unlocked, the BCLK frequencies
from Table 8 will be output. Note that the clock continuity is not maintained when this output format is
set.
CLOCK SYSTEM DIAGRAM
This section presents the relationship between the two master clock types and the switching and
clock dividing functions.
The items in square brackets near the switch and function blocks are the names of write commands.
The Lock/Unlock switch is switched automatically according to the locked/unlocked state of the PLL
circuit.



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