WM8978 datasheet(63/78 Pages) WOLFSON

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WM8978

PP Rev 1.7 January 2005

If jack detection is not enabled (JD_EN=0), the output enables default to all 1’s, allowing the outputs

to be controlled as normal via the normal output enables found in Table 40. Similarly the VMID_EN

signal defaults to 0 allowing the VMID driver to be controlled via the normal enable bit.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

5:4

JD_SEL

Pin selected as jack detection input

00 = GPIO1

01 = GPIO2

10 = GPIO3

11 = Reserved

JD_EN

Jack Detection Enable

0=disabled

1=enabled

GPIO control

8:7

JD_VMID

[7] VMID_EN_0

[8] VMID_EN_1

3:0

JD_EN0

Output enables when selected jack

detection input is logic 0.

[0]= OUT1_EN_0

[1]= OUT2_EN_0

[2]= OUT3_EN_0

[3]= OUT4_EN_0

R13

7:4

JD_EN1

Output enables when selected jack

detection input is logic 1

[4]= OUT1_EN_1

[5]= OUT2_EN_1

[6]= OUT3_EN_1

[7]= OUT4_EN_1

Table 53 Jack Detect Register Control Bits

CONTROL INTERFACE

SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS

The control interface can operate as either a 3-wire or 2-wire MPU interface. The MODE pin

determines the 2 or 3 wire mode as shown in Table 54.

The WM8978 is controlled by writing to registers through a serial control interface. A control word

consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is

accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each

control register.

MODE

INTERFACE FORMAT

Low

2 wire

High

3 wire

Table 54 Control Interface Mode Selection

3-WIRE SERIAL CONTROL MODE

In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on

CSB/GPIO1 pin latches in a complete control word consisting of the last 16 bits.

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