WM8978 datasheet(12/78 Pages) WOLFSON

12 / 78 page

WM8978

Product Preview

PP Rev 1.7 January 2005

Test Conditions

DCVDD=1.8V,

DBVDD=AVDD=SPKVDD=3.3V,

DGND=AGND=SPKGND=0V,

TA=+25

oC,

Slave

Mode,

fs=48kHz,

MCLK=256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

FRAME propagation delay from BCLK falling edge

tDL

ADCDAT propagation delay from BCLK falling edge

tDDA

DACDAT setup time to BCLK rising edge

tDST

DACDAT hold time from BCLK rising edge

tDHT

AUDIO INTERFACE TIMING – SLAVE MODE

Figure 3 Digital Audio Data Timing – Slave Mode

Test Conditions

DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA=+25

oC, Slave Mode, fs=48kHz,

MCLK= 256fs, 24-bit data, unless otherwise stated.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

Audio Data Input Timing Information

BCLK cycle time

tBCY

BCLK pulse width high

tBCH

BCLK pulse width low

tBCL

FRAME set-up time to BCLK rising edge

tLRSU

FRAME hold time from BCLK rising edge

tLRH

DACDAT hold time from BCLK rising edge

tDH

ADCDAT propagation delay from BCLK falling edge

tDD

Note:

BCLK period should always be greater than or equal to MCLK period.

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