LAN91C100FD datasheet(23/68 Pages) SMSC

23 / 68 page

SMSC DS – LAN91C100FD REV. B

Page 23

Rev. 05/31/2000

BANK 0

OFFSET

NAME

TYPE

SYMBOL

COUNTER REGISTER

READ ONLY

ECR

Counts four parameters for MAC statistics. When any counter reaches 15 an interrupt is issued. All counters are cleared

when reading the register and do not wrap around beyond 15.

HIGH

BYTE

NUMBER OF EXC. DEFFERED TX

NUMBER OF DEFFERED TX

LOW

BYTE

MULTIPLE COLLISION COUNT

SINGLE COLLISION COUNT

Each four bit counter is incremented every time the corresponding event, as defined in the EPH STATUS REGISTER bit

description, occurs. Note that the counters can only increment once per enqueued transmit packet, never faster, limiting the

rate of interrupts that can be generated by the counters. For example if a packet is successfully transmitted after one

collision the SINGLE COLLISION COUNT field is incremented by one. If a packet experiences between 2 to 16 collisions,

the MULTIPLE COLLISION COUNT field is incremented by one. If a packet experiences deferral the NUMBER OF

DEFERRED TX field is incremented by one, even if the packet experienced multiple deferrals during its collision retries.

The COUNTER REGISTER facilitates maintaining statistics in the AUTO RELEASE mode where no transmit interrupts are

generated on successful transmissions.

Reading the register in the transmit service routine will be enough to maintain statistics.

BANK 0

OFFSET

NAME

TYPE

SYMBOL

MEMORY INFORMATION REGISTER

READ ONLY

MIR

HIGH

BYTE

FREE MEMORY AVAILABLE (IN BYTES * 256 * M)

LOW

BYTE

MEMORY SIZE (IN BYTES *256 * M)

FREE MEMORY AVAILABLE - This register can be read at any time to determine the amount of free memory. The register

defaults to the MEMORY SIZE upon reset or upon the RESET MMU command.

MEMORY SIZE - This register can be read to determine the total memory size.

All memory related information is represented in 256 * M byte units, where the multiplier M is determined by the MCR upper

byte.

These register default to FFh, which should be interpreted as 256.

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