P89LPC933FDH datasheet(27/75 Pages) PHILIPS

27 / 75 page

9397 750 15113

Product data sheet

Rev. 06 — 20 June 2005

27 of 75

Philips Semiconductors

P89LPC933/934/935/936

8-bit microcontroller with accelerated two-clock 80C51 core

8.7 CCLK wake-up delay

The P89LPC933/934/935/936 has an internal wake-up timer that delays the clock until it

stabilizes depending on the clock source used. If the clock source is any of the three

crystal selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles

plus 60

µsto100 µs. If the clock source is either the internal RC oscillator, watchdog

oscillator, or external clock, the delay is 224 OSCCLK cycles plus 60

µsto100 µs.

8.8 CCLK modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 510 times by conﬁguring a dividing

CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can

retain the ability to respond to events that would not exit Idle mode by executing its normal

program at a lower rate. This can also allow bypassing the oscillator start-up time in cases

where Power-down mode would otherwise be used. The value of DIVM may be changed

by the program at any time without interrupting code execution.

8.9 Low power select

The P89LPC933/934/935/936 is designed to run at 12 MHz (CCLK) maximum. However,

if CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower

the power consumption further. On any reset, CLKLP is logic 0 allowing highest

performance access. This bit can then be set in software if CCLK is running at 8 MHz or

slower.

8.10 Memory organization

The various P89LPC933/934/935/936 memory spaces are as follows:

• DATA

128 bytes of internal data memory space (00H:7FH) accessed via direct or indirect

addressing, using instructions other than MOVX and MOVC. All or part of the Stack

may be in this area.

• IDATA

Indirect Data. 256 bytes of internal data memory space (00H:FFH) accessed via

indirect addressing using instructions other than MOVX and MOVC. All or part of the

Stack may be in this area. This area includes the DATA area and the 128 bytes

immediately above it.

• SFR

Selected CPU registers and peripheral control and status registers, accessible only

via direct addressing.

• XDATA (P89LPC935/936)

‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space

addressed via the MOVX instruction using the SPTR, R0, or R1. All or part of this

space could be implemented on-chip. The P89LPC935/936 has 512 bytes of on-chip

XDATA memory.

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