89LPC925 datasheet(21/49 Pages) PHILIPS

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Philips Semiconductors

P89LPC924/925

8-bit microcontrollers with accelerated two-clock 80C51 core

Product data

Rev. 03 — 15 December 2004

21 of 49

9397 750 14471

8.9.5

Boundary limits interrupt

The A/D converter has both a high and low boundary limit register. After the four

MSBs have been converted, these four bits are compared with the four MSBs of the

boundary high and low registers. If the four MSBs of the conversion are outside the

limit an interrupt will be generated, if enabled. If the conversion result is within the

limits, the boundary limits will again be compared after all 8 bits have been converted.

An interrupt will be generated, if enabled, if the result is outside the boundary limits.

The boundary limit may be disabled by clearing the boundary limit interrupt enable.

8.9.6

DAC output to a port pin with high output impedance

The A/D converter’s DAC block can be output to a port pin. In this mode, the

AD1DAT3 register is used to hold the value fed to the DAC. After a value has been

written to the DAC, the DAC output will appear on the channel 3 pin.

8.9.7

Clock divider

The A/D converter requires that its internal clock source be in the range of 500 kHz to

3.3 MHz to maintain accuracy. A programmable clock divider that divides the clock

from 1 to 8 is provided for this purpose.

8.9.8

Power-down and idle mode

In idle mode the A/D converter, if enabled, will continue to function and can cause the

device to exit idle mode when the conversion is completed if the A/D interrupt is

enabled. In Power-down mode or Total power-down mode, the A/D does not function.

If the A/D is enabled, it will consume power. Power can be reduced by disabling the

A/D.

8.10 Memory organization

The various P89LPC924/925 memory spaces are as follows:

• DATA

128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect

addressing, using instruction other than MOVX and MOVC. All or part of the Stack

may be in this area.

• IDATA

Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via

indirect addressing using instructions other than MOVX and MOVC. All or part of

the Stack may be in this area. This area includes the DATA area and the 128 bytes

immediately above it.

• SFR

Special Function Registers. Selected CPU registers and peripheral control and

status registers, accessible only via direct addressing.

• CODE

64 kB of Code memory space, accessed as part of program execution and via the

MOVC instruction. The P89LPC924/925 has 4 kB/8 kB of on-chip Code memory.

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