89LPC925 datasheet(22/49 Pages) PHILIPS

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Philips Semiconductors

P89LPC924/925

8-bit microcontrollers with accelerated two-clock 80C51 core

Product data

Rev. 03 — 15 December 2004

22 of 49

9397 750 14471

8.11 Data RAM arrangement

The 256 bytes of on-chip RAM are organized as shown in Table 5.

8.12 Interrupts

The P89LPC924/925 uses a four priority level interrupt structure. This allows great

ﬂexibility in controlling the handling of the many interrupt sources. The

P89LPC924/925 supports 13 interrupt sources: A/D converter, external interrupts 0

and 1, timers 0 and 1, serial port Tx, serial port Rx, combined serial port Rx/Tx,

brownout detect, watchdog/real-time clock, I2C, keyboard, and comparators 1 and 2.

Each interrupt source can be individually enabled or disabled by setting or clearing a

bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a

global disable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by

setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An

interrupt service routine in progress can be interrupted by a higher priority interrupt,

but not by another interrupt of the same or lower priority. The highest priority interrupt

service cannot be interrupted by any other interrupt source. If two requests of

different priority levels are pending at the start of an instruction, the request of higher

priority level is serviced.

If requests of the same priority level are pending at the start of an instruction, an

internal polling sequence determines which request is serviced. This is called the

arbitration ranking. Note that the arbitration ranking is only used to resolve pending

requests of the same priority level.

8.12.1

External interrupt inputs

The P89LPC924/925 has two external interrupt inputs as well as the Keypad Interrupt

function. The two interrupt inputs are identical to those present on the standard

80C51 microcontrollers.

These external interrupts can be programmed to be level-triggered or edge-triggered

by setting or clearing bit IT1 or IT0 in Register TCON.

In edge-triggered mode if successive samples of the INTn pin show a HIGH in one

cycle and a LOW in the next cycle, the interrupt request ﬂag IEn in TCON is set,

causing an interrupt request.

If an external interrupt is enabled when the P89LPC924/925 is put into Power-down

or Idle mode, the interrupt will cause the processor to wake-up and resume operation.

Refer to Section 8.15 “Power reduction modes” for details.

Table 5:

On-chip data memory usages

Type

Data RAM

Size (bytes)

DATA

Memory that can be addressed directly and indirectly

128

IDATA

Memory that can be addressed indirectly

256

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