MFC2000 datasheet(238/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

11-6

Conexant

100723A

11.2.6 BRB Synchronization

The Swath Fetcher and the brb_regs blocks operate at SIUCLK frequencies, while the brb_memif, and the Bit

Packer circuits operate at ihsclk frequencies. The reason for this is to control power consumption and noise, as

the higher SIUCLK frequency is not required for operation of the Bit Packer and the BRB Local SRAM Controller.

Because of these different frequencies, a synchronization block is required to allow these blocks to communicate

in a reliable fashion.

11.3 Register Description

Rotation Control Register

Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default

Rotation Control

(RotCtrl)

01FF8061

Rotate Start

(W)

Rotate

Status (R),

1:busy

(Not Used)

(Not Used) Rst. Value

0xxxxxxxb

Read Value

00h

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

Rotation Control

(RotCtrl)

01FF8060

(Not Used)

Packing

Order

0: odd then

even

1: even then

odd

Underrun

0: No

underrun

1: Underrun

occurred.

Packed-byte

status

0: not ready

1: ready

Shuttle

Direction

0: Left to

Right

1: Right to

left

Rst. Value

xxxx0000b

Read Value

00h

Bit 15

To start the bit rotation function, the CPU should write a 1 to this bit

location. Reading this bit location indicates the status of the block

rotation function. 0 = Not busy, 1 = busy. This bit will be set to 0 at the

end of a print swath, and all bit rotation circuits will be reset with the

exception of the BRB registers. If an unrecoverable error condition

occurs within the system, then the BRB block may be reset by creating

a falling edge on the RotateStart bit.

Bit 14-4

Not used

Bit 3

The packing order allows the order of the groups of odd and even bits

to be switched.

Bit 3 = 0 => Odd bit is output first.

Bit 15

n18

n17

n16

n15

n14

n13

n12

n11

n10

Bit 0

18 nozzles

2nd DMA Ch2 halfword

1st DMA Ch2 halfword

Bit 3 = 1 => Even bit is output first

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