MFC2000 datasheet(82/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

4-52

Conexant

100723A

4.4.2.7

External Interrupt Configuration Register

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

EIRQConfig

0x01FF802C

irq16edge

irq13edge

irq11edge

irq2edge

irq16actlo

irq13actlo

irq11actlo

irq2actlo

Rst

Value

00h

Read

Value

00h

Bit 7 – 4:

Write a 1 will configure the corresponding external interrupt to be edge

triggered and write a 0 will configure it to be level triggered.

Bit 3 – 0:

Write a 1 will configure the corresponding external interrupt to be

active low and write a 0 will configure it to be active high.

4.4.2.8

External Interrupt Clear Register

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

EIRQClear

0x01FF802D

(Not Used)

irq21clr

irq10clr

eirq16clr

eirq13clr

eirq11clr

eirq2clr

Rst Value

xx000000b

Read Value

00h

Bit 3 – 0:

Firmware uses these bits to clear the corresponding edge triggered

external interrupt which is latched in the interrupt controller. After

writing a 1 to clear the interrupts, the bits reset themselves to 0.

Bit 5 – 4:

Firmware uses these bits to clear the corresponding internal timer

interrupts. After writing a 1 to clear the interrupts, the bits reset

themselves to 0.

4.4.2.9

Timer1 Register

Address:

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default:

Timer1

0x01FF802F

Timer 1 Value MSB

Rst Value

00h

Read Value

00h

Address:

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default:

Timer1

0x01FF802E

Timer 1 Value LSB

Rst Value

00h

Read Value

00h

Bit 15 – 0:

This is the timer value for the timer1 interrupt. This value will be

loaded in a counter when the timer interrupt bit is enabled. The value

loaded in this register is dependent on the SIUCLK frequency. This

interrupt period can be programmed up to 50 ms with a programmable

resolution. To write a new timer value into the register, the enable bit

in the IRQ/FIQ Enable register must be disabled first; the new timer

value is then written into the register and the enable bit is set to load

the new timer value into the counter.

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