MFC2000 datasheet(85/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

4-55

If a burst of data is sent to the DRAM, the DRAM Controller will run in page mode once the initial access is

completed. The maximum burst length is limited to 8 halfwords (i.e., the maximum burst length coincides with the

CACHE line length) and is controlled by a burst signal that is generated from the SIU. If a burst of data is being

sent to the DRAM, but an octal address boundary occurs, the burst signal will turn off causing a RASn precharge.

It is impossible to go across a page boundary without precharging the RASn signal.

Note:

If a 16-bit wide memory structure is implemented, bursts of data must be 16-bit halfword

bursts. 8-bit byte bursts are only allowed for an 8-bit wide memory structure.

Table 4-11. DRAM Wait State Configurations

Non-Interleaved Modes (8 or 16 bit interfaces)

1 Cycle CASn

30 MHz

-50, -60

3 wait state, PG = 1 wait state

2 Cycle CASn

30 MHz

-50, -60, -70, -80

3 wait state, PG = 2 wait state (read)

2 wait state, PG = 1 wait state (write)

37.5 MHz and 40 MHz

-50, -60

5 wait state, PG = 2 wait state (read)

4 wait state, PG = 1 wait state (write)

37.5 MHz

-70

5 wait state, PG = 2 wait state (read)

4 wait state, PG = 1 wait state (write)

Interleaved Mode (16-bit interface)

30 MHz

-50, -60, -70, -80

3 wait state, PG = 0,1,0 wait state (read)-Even starting

address, non octal boundary

4 wait state, PG=1,0,1 wait state (read)- Odd starting

address, non octal boundary

2 wait state, PG = 1 wait state (write)

37.5 MHz and 40 MHz

-50, -60

5 wait state, PG = 0,1,0 wait state (read)

4 wait state, PG = 1 wait state (write)

37.5 MHz

-70

5 wait state, PG = 0,1,0 wait state (read)

4 wait state, PG = 1 wait state (write)

Note: PG = page mode

4.5.1.1

Memory Bank Structure

DRAM address space can be selected in 2 separate memory blocks (Bank 0: RASn[0] and CASOn[0] (8-bit) or

CASOn[1:0] (16-bit) or CASOn[1:0] and CASEn[1:0] (interleaved), Bank 1: RASn[1] and CASOn[0] (8-bit) or

CASOn[1:0] (16-bit) or CASOn[1:0] and CASEn[1:0] (interleaved). Separate control bits are provided in the

Backup Configuration register to enable and disable (default) each of the memory banks. Each bank has separate

configuration controls and the address ranges of the two memory banks is continuous around the midpoint of the

DRAM memory bank. The RASn[1] starting address is 03000000h and grows larger based on the size of the

memory. The end of the RASn[0] bank ends at 03000000h and grows smaller from that point. The memory range

is programmed through the address multiplexer selections for bank 0 and bank 1 in the DRAMCtrl register.

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