MFC2000 datasheet(52/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

4-22

Conexant

100723A

4.2.2

Name/Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

Cache Control

$01FF8800

N/A

Flush Cache

Global Lock

Lock Mode

Test Mode

Cache Enable

N/A

Rst Value

00h

This register resides in the SIU block. The SIU, upon detecting the set condition for a given bit(s) in this register,

asserts the corresponding control signal(s) to the Cache controller.

Bit 7

Reserved

Bit 6

Flush Cache

Read/writable bit. Writing a 1 to this bit flushes all Valid bits, LRU bits,

and Lock bits in the Cache Tag to zero. It requires 128 cycles to flush

the entire Tag memory area. This bit will be automatically reset upon

completion of the flush operation. Flush does not reset Global Lock or

Cache Enable condition if present.

Bit 5

Global Lock

Read Writable bit. Writing a 1 to this bit locks the entire Cache

memory; a 0 unlocks the Cache. This bit provides a quick way to lock

the entire cache memory.

Bit 4

Lock Mode

Read/writable bit. Writing a 1 to this bit and a 0 to the Cache Enable

bit places the Cache in the Lock Mode. The Cache stays in Lock Mode

until a 0 is written to this bit.

Bit 3

Test Mode

Read/writable bit. Writing a 1 to this bit and a 0 to the Cache Enable

bit sets the Cache into test mode. In test mode, the Cache RAMs and

Tags can be accessed in the same manner as regular memory.

Certain Tag bits are readable only. The Cache stays in Test Mode

until a 0 is written to this bit.

Bit 2

Cache Enable

Read/writable bit. Writing a 1 enables the Cache and the Cache stays

enabled until a 0 is written or a reset is received. Power-up resets to 0

and disables the Cache.

Bit 1

Reserved

Bit 0

Reserved

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