MFC2000 datasheet(325/426 Pages) ETC

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Hardware Description

MFC 2000 Multifunctional Peripheral Controller 2000

100723A

Conexant

17-3

17.3 Functional Description

The PPI contains an interface controller, which consists of: a data receive and transmit latch, run-length encoding

decompression logic, input conditioning logic, and edge detector logic. The RLE decompression is accomplished

through a state machine and additional control logic. There is input conditioning logic to filter the incoming control

signals. The peripheral interface block supports four IEEE 1284 communication modes: compatibility, nibble, byte,

and enhanced capabilities port (ECP) mode. The interface with the DMA controller requires storing data into 8 bit

bytes before transferring to the four half word FIFO for burst operation. There will be a counter within the FIFO

that keeps track of the bytes transferred to the FIFO. There is a control bit allowing FIFO flush to be done. If

firmware detects the end of transfer to the PPI, it can flush the FIFO by forcing the flush bit. The timing of the F/W

flush is based on a fixed time from the last DMA access and the FIFO not empty status and there will be a busy

status bit set by F/W to stop further transmission from the host. The DMA or the interrupt operations are enabled

under the control of the F/W. The PPI has fifteen sources of interrupt that can each be individually enabled or

disabled and they are all ORed together to generate one PPI IRQ interrupt for the CPU.

DATA RECEIVE

LATCH

SLCTINn

STROBEn

AUTOFDn

INITn

STATE MACHINE

sinb

CONTROL

REGISTERS

DATA TRANSMIT

LATCH

FAULTn

SLCTOUTn

ACKn

BUSY

ippid(7:0)

FPPD(7:0)

RPPD(7:0)

oppid(7:0)

strb

afdb

inib

DIGITAL FILTER

DMA FIFOs

IP_BUS

Fack

Rreq

Rack

IP_BUS

DMAREQ

DMARWN

DMAACK

DMA_TC

Freq

Figure 17-1. Parallel Port Interface Controller Block Diagram

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