MFC2000 datasheet(338/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

17-16

Conexant

100723A

17.5 Timing

17.5.1 Compatibility Timing

When this mode of handshaking is enabled, the PPI automatically generates BUSY upon reception of the leading

edge of STROBEn from the host, and latches the logic levels to the ippid bus and AUTOFDn in the Parallel Port

Data Register. The PPI then waits for the STROBEn to de-assert and the Parallel Port Data Register to be read.

After the later of these events occurs, the PPI asserts ACKn for the duration specified in the Parallel Port ACK

Pulse Width Register and then de-asserts ACKn and BUSY to conclude the data transfer.

When data is latched into the Parallel Port Data Register, the PPI controller generates two events: an internal

parallel port DMA request, and a processor interrupt request. Software may alternate between DMA and interrupt

based data transfers. The DMA request remain active until the data is read by either the DMA channel, or the

processor in response to the interrupt request.

If the Forward DMA FIFO has been enabled, the Forward DMA FIFO generates fdmareq after reading the Parallel

Port Data Register and writing the data to its internal half word quad registers. When the fdmack is generated the

DMA channel reads the Forward FIFO internal Registers, ACKn is pulsed, BUSY is deserted, and the fdmack is

cleared.

17.5.1.1 Compatibility Mode Timing Diagram

Host writes data to the data bus

If obusy is not active, the host will assert the istroben low.

Peripheral will assert obusy high to indicate data transfer cycle.

Host will set the istroben and at the rising edge, the peripheral will latch the data .

Peripheral asserts oackn low to acknowledge the transfer and drops the obusy.

IPPID[7:0]

STROBEn

BUSY

ACKn

Latch data Request

Interrupt

Read data Make ACK

pulse

Figure 17-2. Compatibility Mode Timing Diagram

MFC2000 데이터시트(PDF) 338 Page - List of Unclassifed Manufacturers