MFC2000 datasheet(194/426 Pages) ETC

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MFC2000 Multifunctional Peripheral Controller 2000

Hardware Description

7-46

Conexant

100723A

Name/Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default

SPI Status

(SPIStat)

$01FF854D

(Not Used)

Received

ACK

(read only)

Rst. Value

xxxxxxx0b

Read Value

00h

Name/Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

SPI Status

(SPIStat)

$01FF854C

(Not Used)

SID line

(read only)

SIC line

(read only)

Rst. Value

xxxxxx00b

Read Value

00h

Bit 8

Received ACK

This is a read only bit which is only valid after writing a 1 to “WAC” bit

and after verifying that WAC operation is completed, i.e., WAC bit is 0.

After master sends data to slave, master must check if slave has

received the data properly. This checking is done by requesting

acknowledge from slave. In this situation, master is sending a clock

pulse, and capture the acknowledge on SID line while SIC is high.

This is the acknowledge stored in bit 8.

Bit 1

SID – Serial Input Data line

This is a read only bit which comes directly from the SID pin.

Bit 0

SIC – Serial Input Clock line

This is a read only bit which comes directly from the SIC pin.

Name/Address

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

Bit 8

Default

SPI Configuration

(SPIConfig)

$01FF88C1

(Not Used)

Rst. Value

xxh

Read Value

00h

Name/Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Default

SPI Configuration

(SPIConfig)

$01FF88C0

Manual

Operation

(Not Used)

SPI

Interrupt

Enable

Clock Mode Clk

Divider[1]

Clk

Divider[0]

Rst. Value

0xxx0000b

Read Value

00h

Bit 7

Manual Operation

By setting this bit, firmware can control the SID and SIC directly by

writing to bit 1 and bit 0 of SPI_Ctrl register.

Bit 3

SPI Interrupt Enable

By setting this bit, the interrupt from SPI is enabled. At the end of

REA, STA, STO, RAC, WAC, or WRI operation, the interrupt will be

active in order to indicate the completion of operation. Once the

firmware has serviced this interrupt, it can be cleared by writing a 1 to

bit 1 of ‘VSCIRQStatus’ register.

Bit 2

Clock Mode

Bit 1-0

Clock Divider[1:0]

MFC2000 데이터시트(PDF) 194 Page - List of Unclassifed Manufacturers

MFC2000 데이터시트(HTML) 194 Page - List of Unclassifed Manufacturers

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