AR0141CS datasheet(5/48 Pages) ONSEMI

5 / 48 page

AR0141CS

www.onsemi.com

Figure 3. Typical Configuration: Parallel Pixel Data Interface

VAA_PIX

VAA

VDD_PLL

VDD

VDD_IO

From Controller

Master Clock

(6 − 50 MHz)

Digital

I/O

Power1

Digital

Core

Power1

PLL

Power1

Analog

Power1

SDATA

SADDR

SCLK

TRIGGER

OE_BAR

RESET_BAR

TEST

DOUT [11:0]

PIXCLK

FRAME_VALID

LINE_VALID

Analog

Power1

DGND

AGND

Digital

Ground

Analog

Ground

VAA VAA_PIX

VDD_PLL

VDD_IO VDD

EXTCLK

To Controller

Notes:

1. All power supplies must be adequately decoupled.

2. ON Semiconductor recommends a resistor value of 1.5 kW, but a greater value may be used for slower two−wire speed.

3. The serial interface output pads and VDD_SLVS can be left unconnected if the parallel output interface is used.

4. ON Semiconductor recommends that 0.1 mF and 10 mF decoupling capacitors for each power supply are mounted as

close as possible to the pad. Actual values and results may vary depending on layout and design considerations.

Check the AR0141CS demo headboard schematics for circuit recommendations.

5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital

power planes is minimized.

6. I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage current.

7. The EXTCLK input is limited to 6−50 MHz.

SHUTTER

FLASH

Table 3. BALL DESCRIPTIONS, 9 X 9 MM, 63−BALL iBGA

Name

iBGA Pin

Type

Description

SLVS0_N

Output

HiSPi serial data, lane 0, differential N

SLVS0_P

Output

HiSPi serial data, lane 0, differential P

SLVS1_N

Output

HiSPi serial data, lane 1, differential N

SLVS1_P

Output

HiSPi serial data, lane 1, differential P

STANDBY

Input

Standby (active high)

VDD_PLL

Power

PLL power

SLVSC_N

Output

HiSPi serial DDR clock differential N

SLVSC_P

Output

HiSPi serial DDR clock differential P

SLVS2_N

Output

HiSPi serial data, lane 2, differential N

SLVS2_P

Output

HiSPi serial data, lane 2, differential P

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